module ysyx_22040213_memory_port (
	  input rst,
	  // addr
	  input [63:0] maddr,
	  //req
	  input lm_en,
	  input sm_en,
	  //end req
	  input  [2:0] exe_funct3,
	  input  [2:0] mem_funct3,
	  input  [63:0] mwdata,
	  output reg [63:0] o_data_mrdata,
	  output reg data_addr_ok,
	  output reg data_data_ok,
	  //clint//
	  output clint_wen,
	  output clint_ren,
	  output clint_addr,
	  output [63:0] clint_wdata,
	  output clint_hit,

	  //sram port  
	  output reg o_data_wr,
	  output reg o_data_req,
	  output reg [2:0] o_data_size,
	  output reg [63:0] o_data_addr,
	  output reg [7:0] o_data_wstrb,
	  output reg [63:0] o_data_wdata,

	  input i_data_addr_ok,
	  input i_data_data_ok,
	  input [63:0] i_data_rdata
);
`define CLINT_START 64'h02000000
`define CLINT_MTIMECMP (`CLINT_START + 64'h4000)
`define CLINT_MTIME    (`CLINT_START + 64'hbff8)
	assign clint_hit = (maddr == `CLINT_MTIMECMP) || (maddr == `CLINT_MTIME);
	assign clint_wen = sm_en && clint_hit;
	assign clint_ren = lm_en && clint_hit;
	assign clint_addr = (maddr == `CLINT_MTIMECMP) ? 1'b0 : 1'b1;
	assign clint_wdata = mwdata;
	//port//
	wire [2:0] data_size;
	wire [7:0] data_wstrb;
	reg [63:0] mrdata;
	MuxKey #(4, 3, 3) i0 (data_size, exe_funct3, {
		3'b000, 3'b000,	
		3'b001, 3'b001,
		3'b010, 3'b010,
		3'b011, 3'b100
		});


	MuxKey #(4, 3, 8) i1 (data_wstrb, exe_funct3, {
		3'b000, 8'h01,	
		3'b001, 8'h03,
		3'b010, 8'h0f,
		3'b011, 8'hff
		});

	always @(*)begin
	  if(rst)begin
	    o_data_wr = 1'b0;
	    o_data_req = 1'b0;
	    o_data_size = 3'b0;
	    o_data_addr = 64'h0000000080000000;
	    o_data_wstrb = 8'b0;
	    o_data_wdata = 64'b0;
	    o_data_size  =3'b0;
	    o_data_wstrb = 8'b0;
	    data_addr_ok = 1'b0;
	    data_data_ok = 1'b0;
	    mrdata = 64'b0;
	  end
	  else begin
	    o_data_wr = sm_en ? 1'b1 : 1'b0;
	    o_data_req = (sm_en || lm_en) && !clint_hit; 
	    o_data_wdata = mwdata;
	    o_data_addr = maddr;
	    o_data_size = data_size;
	    o_data_wstrb = data_wstrb;
	    mrdata = i_data_rdata;
	    data_addr_ok = i_data_addr_ok;
	    data_data_ok = i_data_data_ok;
	  end
	end
	MuxKey #(7, 3, 64) i2 (o_data_mrdata, mem_funct3, {
		3'b000, {{56{mrdata[15]}},mrdata[7:0]},	
		3'b001, {{48{mrdata[15]}},mrdata[15:0]},	
		3'b010, {{32{mrdata[31]}},mrdata[31:0]},
		3'b011, mrdata,
		3'b100, {{56{1'b0}},mrdata[7:0]},
		3'b101, {{48{1'b0}},mrdata[15:0]},
		3'b110, {{32{1'b0}},mrdata[31:0]}
		});
endmodule
